Re: gEDA-dev: icarus/ivtest/contrib8.2.v

[Steven Wilson <stevew-at-NOSPAMintrinsix_dot_com>]

Evan,

I ran it through NCVERILOG, Verilog-XL, and CVER just to check. They all
liked the code to various levels.

What I see below is both an implicit wire named "c" and a module named
"c".   The module names conflict -but this is legal verilog.  (not
clever - but legal).

Verilog is going to assume an implicit wire of 1 bit. 

Further - if you look at the definitions of module a we see a one bit
input, and module d we see input d is also a single bit in width.

I guess I don't see any issues here - can you take what I've pointed out
above and tell me where you think we differ?

Steve Wilson

Evan Lavelle wrote:
> This is a short test which checks named port association and
> concatenation in module declarations and instantiations, from Stefan
> Thiede at Philips. There seems to be an issue with it - has anyone run
> it on any other sims?
>
> Two of the modules are instantiated with an actual of 'c', but 'c'
> isn't declared in 'test' (ie. 'a a1(.a(c));'. ModelSim, ISE and
> iverilog all ignore the identifier ('c') but assume that it's 1-bit.
> It seems to me that all 3 simulators have got it wrong - have I missed
> something?
>
> Evan
> =========================================================================
> /*
>  * Copyright (c) 1998 Philips Semiconductors
> (Stefan.Thiede@sv.sc.philips.com)
>  *
>  *    This source code is free software; you can redistribute it
>  *    and/or modify it in source code form under the terms of the GNU
>  *    General Public License as published by the Free Software
>  *    Foundation; either version 2 of the License, or (at your option)
>  *    any later version.
>  *
>  *    This program is distributed in the hope that it will be useful,
>  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
>  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>  *    GNU General Public License for more details.
>  *
>  *    You should have received a copy of the GNU General Public License
>  *    along with this program; if not, write to the Free Software
>  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
> 02111-1307, USA
> */
> // 9/7/99 - SDW - Added a PASSED message - no functional checking needed
>
>
> module test();
> wire [1:0] a;
> wire [9:0] b;
> wire [0:9] d;
> a       a1(.a(c));
> b       b1(.a(a[0]));
> c       ci(.a({a, b}));
> d       d1(.a({d[0:9], a[1:0]}), .d(c));
> f       f(a);
> a       a3(a[1]);
> a       a4({a[1]});
> g       g({a,b});
> e       e();
>
> initial
>   $display("PASSED");
> endmodule
>
> module a(a);
> input a;
> endmodule
>
>
> module b(.a(b));
> input b;
> endmodule
>
> module c(.a({b, c}), );
> input [10:0] b;
> input c;
> endmodule
>
> module d(.a({b, c}), d);
> input [10:0] b;
> input c, d;
> endmodule
>
> module e();
> endmodule
>
> module f({a, b});
> input a, b;
> endmodule
> module g(a);
> input [11:0] a;
> endmodule
>
>
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