gEDA-dev: icarus verilog clock edge at t=0 question

[Lennert Buytenhek <buytenh-at-NOSPAMwantstofly_dot_org>]

Hi,

Another question (please tell me if I'm being stupid) -- if I
initialise a register to 1, any sub-modules that I pass this register
see a posedge at t=0, but the module in which the register is declared
does not.

I.e. if I have the following test code:

	module sub(clk, submodule_rising, submodule_falling);
		input	clk;
		output	submodule_rising;
		output	submodule_falling;

		reg	submodule_rising = 1'b0;
		reg	submodule_falling = 1'b0;

		always @(posedge clk) begin
			submodule_rising <= #1 1'b1;
		end

		always @(negedge clk) begin
			submodule_falling <= #1 1'b1;
		end
	endmodule

	module test;
		reg	clk = 1'b1;
		reg	topmodule_rising = 1'b0;
		reg	topmodule_falling = 1'b0;
		wire	submodule_rising;
		wire	submodule_falling;

		always @(posedge clk) begin
			topmodule_rising <= #1 1'b1;
		end

		always @(negedge clk) begin
			topmodule_falling <= #1 1'b1;
		end

		sub sub(clk, submodule_rising, submodule_falling);

		initial begin
			$dumpfile("clkrising.vcd");
			$dumpvars();

			clk = 1'b1;

			@(posedge clk);
			@(posedge clk);

			@(posedge clk)
				$finish;
		end

		always begin
			clk = #5 ~clk;
		end
	endmodule

I had expected the following behavior:
- topmodule_rising to become 1'b1 at t=11
- topmodule_falling to become 1'b1 at t=6
- submodule_rising to become 1'b1 at t=11
- submodule_falling to become 1'b1 at t=6

Instead, it seems that submodule_rising becomes 1'b1 at t=1, so
somehow it is picking up a posedge clk at t=0.

topmodule_rising does _not_ seem to pick up a posedge clk at t=0,
so that signal _does_ only become 1'b1 at t=11.

Similarly, if I do "reg clk = 1'b0;" and "initial clk = 1'b0;",
the submodule picks up a negedge clk at t=0, but the top-level
module does not.

Are my expectations wrong?


thanks,
Lennert


_______________________________________________
geda-dev mailing list
geda-dev@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev