Re: gEDA-dev: Fwd: google soc

[Steve Meier <smeier-at-NOSPAMalchemyresearch_dot_com>]

John is on the right track.

PCB might not need to read schematics but PCB and gschem share net list
files already. Plus, high devices such as FPGA's have multiple ways of
using their pins. Many of the IO pins can be single ended io,
differential io, differential receivers or transmitters. To make matters
more complex, the io is borken up into multiple banks of which each bank
can be a different voltage level or even logic level type. Now to use
these we design a schematic with symbols we then generate a netlist and
drop the netlist into pcb and what do we have? we have a complex mess.
So we try to organize the mess by swapping pins or pairs of pins
(differential io don't mix your transmitters with your receivers).
Wouldn't it be nice if our symbols were capable of deffining how the
pins can and are used? Wouldn't it be nice if you could at the layout
time be able to ask the layout program show me which pin pairs this pin
and its counter part can be swapped with.... because they are on the
same bank and are receivers or transmitters. This is where pcb and geda
could be sharing the same data structures with this problem resolved.

I just spent the last couple of weeks looking over the shoulder of a
person using power pads (?) It doesn't seem to have this capablity
either... wouldn't it be nice to be able to do things the competion can't?

Add to this... simulation includding trace lengths with routing (tdr).
Just seems to me that their are hudge advantages for this group of
programs to be better at communicating. So on the subject of if your
going to open a file while have a dozen different implementations of
parsing the file? A dozen opportunities to break things as file
structures evolve?

Steve Meier

John Griessen wrote:
> DJ Delorie wrote:
>   
>>> Does PCB use libgeda?
>>>       
>> Why would pcb need to read schematics?
>>     
>
> I say there's never a way to predict how someone odd
> could come up with a high performance flow of doing things...
> So, "Why not?" is my favorite attitude on this.
>
> Maybe an
> antenna and RF front end designer would make a layout-driven
> workflow instead of schematic-driven?
>
>  From the chip design viewpoint, your cell boundaries
> are unreal, so you could easily decide to rework them in a layout-driven way
> and create new schematics to match.  Once we have low effort hierarchy
> handling in gschem/PCB/gnetlist I think it's natural to want it to
> be definable from any starting point -- and to be able to copy/paste parts and redefine
> modules quickly.  And one way would be to generate a new netlist from a reworked
> layout cell, then a schematic to match.
>
> John Griessen
>
>
> _______________________________________________
> geda-dev mailing list
> geda-dev@moria.seul.org
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
>
>   



_______________________________________________
geda-dev mailing list
geda-dev@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev