gEDA-dev: Icarus verilog EDIF question

["Chris H" <bitmechanic-at-NOSPAMhotmail_dot_com>]

Hello,

I'm using the EDIF target, i.e. -tedif

I present the two cases:

    // Case 1: DFF with async clear active high
    always @ (posedge Clk or posedge Rst) begin
        if (Rst)
            Q <= 1'b0;
        else
            Q <= D;
    end

    // Case 2: DFF with async clear active low
    always @ (posedge Clk or negedge Rst) begin
        if (~Rst)
            Q <= 1'b0;
        else
            Q <= D;
    end

For Case 1 the EDIF will show a DFF with active high Aclr. For Case 2 EDIF 
will also show a DFF with active high Aclr, and an inverter will be added an 
attached to Aclr.  It would be preferable if EDIF used the 'polarity Invert' 
attribute on the Aclr port instead of adding the inverter. This may be even 
more 'correct' in terms of the LPM spec but I'm not sure.

In my library I only have a DFF with *active low* Aclr. Having the polarity 
attribute makes it possible for back-end tools to handle this correctly.  
Otherwise I need to find a way to remove the added inverters every time I 
generate EDIF which is yucky.

I've looked at the source code but it's not readily apparent to me where the 
inverter gets synthesized. I'd be happy to add a EDIF option to add the 
polarity attribute instead if someone could tell me which source code files 
to look at.

Thanks!
Chris

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