Re: gEDA-dev: Run a Verilog test for me

[Stephen Brickles using shaun <stephen-at-NOSPAMmlp_dot_intersil_dot_com>]

stephen> vcs +v2k foo.vl
*** Using loader /usr/ccs/bin/ld instead of cc ...
                         Chronologic VCS (TM)
            Version Y-2006.06 -- Tue Dec 11 15:46:54 2007
               Copyright (c) 1991-2006 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'foo.vl'
Top Level Modules:
       tb
No TimeScale specified

   ***   $sdf_annotate() version 1.2R
   ***    SDF file: "ivltests/sdf5.sdf"
   ***    Annotation scope: tb
   ***    No MTM selection argument specified
   ***    No SCALE FACTORS argument specified
   ***    No SCALE TYPE argument specified
   ***    MTM selection defaulted to "TOOL_CONTROL":
               (+typdelays compiled, TYPICAL delays selected)
   ***    SCALE FACTORS defaulted to "1.0:1.0:1.0":
   ***    SCALE TYPE defaulted to: "FROM_MTM"
   ***    Turnoff delay: "FROM_FILE"
   ***    Approximation (mipd) policy: "MAXIMUM"

   ***    SDF annotation begin: Tue Dec 11 15:47:17 2007


SDF Info: +pulse_r/100, +pulse_e/100 in effect
SDF Warning in instance tb.dut of module XOR20:
ivltests/sdf5.sdf:22, SDF Warning: IOPATH B Q  not found
SDF Warning in instance tb.dut of module XOR20:
ivltests/sdf5.sdf:23, SDF Warning: IOPATH B Q  not found

          Total errors: 0
          Total warnings: 2
   ***    SDF annotation completed: Tue Dec 11 15:47:18 2007


Starting vcs inline pass...
2 modules and 0 UDP read.
recompiling module XOR20
recompiling module tb
Both modules done.
if [ -x ../simv ]; then chmod -x ../simv; fi
/usr/ccs/bin/ld  -o ../simv  /home/shaun/stephen/.bin/vcs/sparcOS5/lib/crt1.o 
/home/shaun/stephen/.bin/vcs/sparcOS5/lib/crti.o  5NrI_d.o 5NrIB_d.o YuN7_1_d.o 
jUh1_1_d.o SIM_l.o  /home/shaun/stephen/.bin/vcs/sparcOS5/lib/libvirsim.a -lnsl 
-lsocket -ldl     /home/shaun/stephen/.bin/vcs/sparcOS5/lib/libvcsnew.so     -lm 
-lc  -ldl  /home/shaun/stephen/.bin/vcs/sparcOS5/lib/crtn.o   
../simv up to date
CPU time: 0 seconds to compile + 1 seconds to link



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