Re: gEDA-dev: Run a Verilog test for me

[Stephen Brickles using shaun <stephen-at-NOSPAMmlp_dot_intersil_dot_com>]

stephen> ncverilog foo.vl
ncverilog: 05.70-s001: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
file: foo.vl
	module worklib.XOR20:vl
		errors: 0, warnings: 0
	module worklib.tb:vl
		errors: 0, warnings: 0
		Caching library 'worklib' ....... Done
	Elaborating the design hierarchy:
	Reading SDF file from location "ivltests/sdf5.sdf"
	Writing compiled SDF file to "sdf5.sdf.X".
	Annotating SDF timing data:
		Compiled SDF file:     sdf5.sdf.X
		Log file:              
		Backannotation scope:  tb
		Configuration file:    
		MTM control:           
		Scale factors:         
		Scale type:            
ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH 
(posedge B) Q) of instance tb.dut of module XOR20 <./ivltests/sdf5.sdf, line 
22>.
ncelab: *W,SDFNEP: Failed Attempt to annotate to non-existent path (IOPATH 
(negedge B) Q) of instance tb.dut of module XOR20 <./ivltests/sdf5.sdf, line 
23>.
	Annotation completed with 0 Errors and 2 Warnings
	Building instance overlay tables: .................... Done
	Generating native compiled code:
		worklib.tb:vl <0x658f3a1c>
			streams:   4, words:   674
	Loading native compiled code:     .................... Done
	Building instance specific data structures.
	Design hierarchy summary:
		             Instances  Unique
		Modules:             2       2
		Primitives:          1       1
		Timing outputs:      1       1
		Registers:           2       2
		Scalar wires:        3       -
		Initial blocks:      1       1
		Pseudo assignments:  2       2
	Writing initial simulation snapshot: worklib.tb:vl
Loading snapshot worklib.tb:vl .................... Done
ncsim> source /apps/ius/tools/inca/files/ncsimrc
ncsim> run
                   0 A=x, B=x, Q=x
                  10 A=1, B=1, Q=x
                  11 A=1, B=1, Q=0
                  20 A=1, B=0, Q=0
                  21 A=1, B=0, Q=1
Simulation complete via $finish(1) at time 30 NS + 0
./foo.vl:34       #10 $finish;
ncsim> exit



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