gEDA: Re: Verilog integer bits

[James Lee <jml-at-NOSPAMseva_dot_com>]

I was chatting with one of the editors of the IEEE standard, and he
suggested that is it 32 bits as a minimum and can be more implemenation
dependant.
 

At 03:53 PM 6/7/99 -0700, Stephen Williams wrote:
>
>jml@seva.com said:
>> Assuming a standard 32 bit machine, ofcourse if we were on a 36 bit
>> machine the answer would be 1. 
>
>The conclusion here is that sign extension does not occur, so the only
>difference (I think) between signed and unsigned arithmetic is the results
>of the comparison operators. And even they can be coerced into working
>in an unsigned universe.
>
>And as for the machine being 32bit, I do not think that matters. Each
>bit of the integer can have 4 possible values (not to mention strengths)
>so the host computer is doing the work bit by bit anyhow. I had considered
>supporting unlimited integers (using context to guess how many bits are
>really needed) but that would only work in a sign-extended world.
>
>At least, that's what *my* machine is doing.
>
>-- 
>Steve Williams                "The woods are lovely, dark and deep.
>steve@icarus.com              But I have promises to keep,
>steve@picturel.com            and lines to code before I sleep,
>http://www.picturel.com       And lines to code before I sleep."
>
>
>
>
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  James M. Lee                                    jml@seva.com
  Seva Technologies, Expert EDA Services   http://www.seva.com
  200 Brown Road, Ste 103, Fremont, CA 94539    (510) 249-9085
  Author "Verilog Quickstart" ISBN 0-7923-9927-7
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