Re: gEDA: Re: Verilog integer bits

[David Cary <d_dot_cary-at-NOSPAMieee_dot_org>]

I think I read
  Clive "Max" Maxfield http://ro.com/~bebopbb
say something about representing 32 different hardware bits ( with values
of 0, 1, X ) in 2 or 3 (?) different 32 bit variables, such that common
boolean operations like AND and OR could be quickly done in parallel. I
seem to remember thinking it was pretty clever, but I've forgotten the
specific details.

So, at least in this case, the host computer is *not* doing the work bit by
bit.
(There may be other cases, such as adding 2 registers where some values are
X, where the host computer may have to work bit by bit).

It does seem kinda silly that description of a piece of hardware might be
compiled into a functionally different piece of hardware depending on which
Verilog compiler (32 bit or 64 bit) one used.

>From: Stephen Williams <steve@icarus.com>
...
>And as for the machine being 32bit, I do not think that matters. Each
>bit of the integer can have 4 possible values (not to mention strengths)
>so the host computer is doing the work bit by bit anyhow. I had considered
>supporting unlimited integers (using context to guess how many bits are
>really needed) but that would only work in a sign-extended world.
>
>At least, that's what *my* machine is doing.

--
David Cary "mailto:d.cary@ieee.org" "icbmto:N36 08.830' W97 03.443'"
  http://www.rdrop.com/~cary/
Future Tech, Unknowns, machine vision ><> <*> O-