Re: gEDA: Re: Verilog integer bits

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

d.cary@ieee.org said:
> So, at least in this case, the host computer is *not* doing the work
> bit by bit.

Well, implementation details may allow one to vectorize the processing
of the simulation, but it is still in principle true that it takes more
then just a host integer word to make a Verilog integer go.

I just think that the integer type is a bit if a confusion in Verilog,
and it really doesn't provide the opportunities for optimization that
a Verilog user might think.

And by the way, I haven't even mentioned switch level modeling yet:-)


d.cary@ieee.org said:
> It does seem kinda silly that description of a piece of hardware might
> be compiled into a functionally different piece of hardware depending
> on which Verilog compiler (32 bit or 64 bit) one used.

Yeah, but as Verilog programmers, we just need to learn to live with it.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
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http://www.picturel.com       And lines to code before I sleep."