gEDA: Warnings from ivl

[Jeff McNeal <jmcneal-at-NOSPAMlevel1_dot_com>]

Some warnings that I'd like to see.

1. sensitivity list issues.  Did I leave something out of the
sensitivity list, and what signal. This should be something that can be
disabled (when I only want clk)  It would be great if ivl could remember
which process ( in VHDL) I said was OK and which weren't

2. Bit width mismatch
        wire [7:0] a;
        a <= b4'0;

3. Case statements.  Missing cases, no default

and some others I can't think of right now.

Jeff