Re: gEDA: Icarus Verilog RFC

[Stefan Thiede <Stefan_dot_Thiede-at-NOSPAMsv_dot_sc_dot_philips_dot_com>]

Hi Steve,

here are my 2 cents worth of thoughts

1) Get the last "unimplemented" features in. (see list below)
2) Update ivlpp to be able to read -f verilog input files.
   This will open up the can of worms, since with this feature I can
   run ivl on all our projects.
3) Change the identifier storage to a hashtable.
   As soon as one want's to use ivl for gatelevel netlists, ivl's 
   memory consumption goes up.

Keep up the brilliant work,
 
Stefan

 Ranges in parameter definition are not supported.
   These might not be in the standart, but are supported by Verilog-XL
   and synopsys, so they're in the "unofficial" defacto standard and
   widely used.
 Sorry, `timescale not supported.
 Sorry, disable statements not supported.
 Sorry, procedural continuous assign not supported.
 warning -- casex not properly supported, using case.
 // synopsys translate_on
 // synopsys translate_off
    are widely used

Stephen Williams wrote:
> 
> I was just now able to compile and execute user defined functions
> (behavioral only) and I'm starting to think that I should be making
> a stable release soon. Functions were really the last thing holding
> me back.
> 
> So at this point I would like to hear about the most pressing issues
> that would (in your mind) keep this from being a usable release.
> Once I make this stable release, I want to switch gears and work
> mostly on synthesis, so I would like to get simulation more or less
> good enough from a feature set point of view.
> 
> (Obviously, I will continue fixing bugs even after the release.)
> 
> Let fly, so that I know what the needs are and I can more usefully
> schedule my time.
> --
> Steve Williams                "The woods are lovely, dark and deep.
> steve@icarus.com              But I have promises to keep,
> steve@picturel.com            and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."

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