gEDA: Icarus Verilog todo list

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Based on the response I got so far, this is the list of must-have items
for Icarus Verilog (that it doesn't currently have) that I expect to go
into the first stable release. Features that it currently supports, I
expect it to handle correctly. Tell me if it doesn't already.

- bit ranges for parameters

- casex/casez

- VCD (This may prove difficult)

- Elaborate and simulate structural +, - and *, and all the bitwise and
  boolean binary and unary operators.

- delayed non-blocking procedural assignments.

There are a few other features that I would also like to see implemented,
but I don't want to hold up a release for. I would love to have help with
these things in particular. (Actually, help with the above items is
encouraged as well.)

- synopsys style command files

     I think that these can be mostly handled in the driver script.
     The command file is essentially a list of command line parameters
     written into a file instead of typed on the command line.

- XNF synthesis of DFF with complex combinatorial expressions as input

     I'm starting to move the internal netlist towards LPM style objects,
     so this will become easier with time.

- all the rest of IEEE1364-1995 and -2000:-)

I want to limit the next (first!) stable release to what can be accomplished
within the next month. Given my work schedule, even the given short list
is ambitious, but that's what it'll take.

Comments?
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."