Re: gEDA: Icarus Verilog todo list

[Jeff McNeal <jmcneal-at-NOSPAMlevel1_dot_com>]

A wish from a verilog user.

We often run sims that take several days on our servers.  One chip took 10 mins
of wall clock time for the chip to come out of reset (lots of analog).   Some of
the verilog simulators will allow you to load a design with a "state".  You can
compile the design, and then set all the internal and external nodes to a state,
something that is stored in a file somewhere.  In our case we would run the chip
till it came out of reset and was ready to "run", then save the state of the
chip.  this could then be loaded by all subsequent sims on the same RTL, saving
tons of time.

It would be great if IVL could do this too.  The VCD thing reminded me of that,
since VCD will need the state of every node in the chip.

Jeff McNeal
Bend OR, USA