Re: gEDA: Icarus Verilog todo list

[Andrew Bardsley <bardslea-at-NOSPAMcs_dot_man_dot_ac_dot_uk>]

On Fri, 3 Sep 1999, Jeff McNeal wrote:

> A wish from a verilog user.
> 
> We often run sims that take several days on our servers.  One chip took 10 mins
> of wall clock time for the chip to come out of reset (lots of analog).   Some of
> the verilog simulators will allow you to load a design with a "state".  You can
> compile the design, and then set all the internal and external nodes to a state,
> something that is stored in a file somewhere.  In our case we would run the chip
> till it came out of reset and was ready to "run", then save the state of the
> chip.  this could then be loaded by all subsequent sims on the same RTL, saving
> tons of time.

This sounds like a good idea.

We've just lost a simulation due to power loss.  The power
was only out for a fraction of a second, unfortunately the
simulation (a processor validation suite) had been running for a month.

- Andrew
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