gEDA: Re: IVL lexical problem/patch

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

(I'm including geda-dev in the dialog, because I think it is of general
interest.)

 1.  Verilog identifiers with '$' in them mess up vvm,
     since '$' can't go in C++ identifiers.  One can
     argue that this is vvm's problem and that mangle()
     should handle it, but:

 2.  Escaped identifiers have the same problem.


pmonta@halibut.imedia.com said:
> After stewing about this, I thought it might be best to premangle
> identifiers in the lexer; this way no core code needs to be touched. 

The problems you describe should *definitely* be handled by a target
specific mangler. Different targets have different identifier constraints.
For example:

	C++ has well known identifier limits.

	EDIF has even tighter constraints, but has the (rename ...)
	construct so that the unmangled name can be preserved when
	being passed to tools.

	Verilog output has identifier escaping, as you note.

It is best to keep accurate names for identifers as long as possible,
so the internal netlist supports arbitrary strings. I have no problem
with the core carrying identifiers exactly how they are entered in the
design.

The target specific manglers are not part of the "core", they are part
of the code generators. Or at least, that's how I see it.

You are right that ivl doesn't handle escaped identifiers correctly,
even when matching symbols internally. I'll try to fix that.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."