Re: gEDA: Verilog: empty statements, more tests

[Guy Hutchison <ghutchis-at-NOSPAMpacbell_dot_net>]

> Is it legal to implicity declare a wire using a named port
> within a module instantiation?  This construct occurs in
> some code, but I haven't chased the grammar; VCS accepts it
> though, hm.

I believe it is legal.  You can also implicitly declare a bussed wire in a port
by declaring name[n:0].  emacs verilog-mode makes extensive use of this
feature, so I assume it's legal...

OTOH, vcs happily parses all kinds of things that XL fatals on...  Multiple
declarations of the same wire, for one.

  - Guy