Re: gEDA: Verilog: empty statements, more tests

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

pmonta@halibut.imedia.com said:
> This small patch fixes empty statements in case items and
> conditionals.

Patch looks obviously correct, and I applied it. Thanks.


pmonta@halibut.imedia.com said:
> Is it legal to implicity declare a wire using a named port within a
> module instantiation?

Do you mean:
    module foo (.a(b));
        // Do you expect a to be implicit?
    endmodule;

I think not. Specifically, what is the direction of an implicitly declared
port. From IEEE 1364-1995 Section 12.3.2 Port declarations:

    "Each port listed in the list of ports for the module definition
    *shall* be declared in the body of the module as an input, output,
    or inout (bidirectional)." [emphasis added]

The word "shall" has specific meaning in an IEEE standard. It means that
you must declare the direction of "a".

On the other hand, I think that "b" may be implicitly declared, as it
is not a port but an internal net or register. If it is implicit, it is
a wire with width 1.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
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