[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

gEDA: Verilog: misc. elaboration



Briefly, some things not yet supported by elaboration:

 - nested tasks (though there does seem to be scoping stuff in pform*.cc)
 - mem[x] <= y (though mem[x] = y is okay)
 - if (n) blah; where n is an integer---can't set width to 1

Cheers,
Peter Monta   pmonta@imedia.com
Imedia Corp.