gEDA: Verilog: parse error

[Peter Monta <pmonta-at-NOSPAMhalibut_dot_imedia_dot_com>]

The following gives a parse error.  Also with 'bz, but
1'bx and 1'bz work, as do 'b0 and 'b1.  Plain "a = 'bx",
without the delay, also works.

module main;
  reg a;
  initial
    a = #1 'bx;
endmodule

Cheers,
Peter Monta   pmonta@imedia.com
Imedia Corp.