[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: gEDA: Verilog: parse error

To: geda-dev-at-NOSPAMgeda_dot_seul_dot_org
Subject: Re: gEDA: Verilog: parse error
From: Stephen Williams <steve-at-NOSPAMicarus_dot_com>
Date: Thu, 09 Sep 1999 20:42:42 -0700
In-Reply-To: Your message of "Thu, 09 Sep 1999 15:46:09 PDT." <199909092246.PAA14402@halibut.imedia.com>
Reply-To: geda-dev-at-NOSPAMseul_dot_org
Sender: owner-geda-dev-at-NOSPAMseul_dot_org

module main;
  reg a;
  initial
    a = #1 'bx;
endmodule

I checked. I read it three times, and stared the standard to death.
I think it *is* a syntax error. Can anybody tell me why?-)
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Follow-Ups:
- Re: gEDA: Verilog: parse error
  - From: Peter Monta

References:
- gEDA: Verilog: parse error
  - From: Peter Monta

Prev by Date: Re: gEDA: Test supervisor RFC
Next by Date: Re: gEDA: Verilog: ternary test code
Prev by thread: gEDA: Verilog: parse error
Next by thread: Re: gEDA: Verilog: parse error
Index(es):
- Date
- Thread