Re: gEDA: Verilog: parse error

[Peter Monta <pmonta-at-NOSPAMhalibut_dot_imedia_dot_com>]

> module main;
>   reg a;
>   initial
>     a = #1 'bx;
> endmodule
>
> I checked. I read it three times, and stared the standard to death.
> I think it *is* a syntax error. Can anybody tell me why?-)

The draft 1364.lang.pdf is all I have access too, so let's see---we
have this unsized binary number "'bx", which page 8 says is okay
(the non_zero_size is optional).  Page 10 has some examples, one
of which is "f = 'hx".

Then there's a procedural blocking assignment with delay, in this
case a delay of 1 tick.  Page 115 has the grammar; there's an optional
delay_or_event_control, and page 117 has some examples (all of which
have explicity sized constants in their rhs's---oh well).

Aha, I think the lexer is melding the delay and the constant, giving
the nonsensical "a = #(1'bx);" to the parser.  That's correct from
the lexer standpoint---it should and does do "maximal munch" if
I remember the old saying right---but this is a real ambiguity then.
Why doesn't the standard mention it?

Well, it's too complex for the lexer to construct some DELAY object
to give to the parser, but I'm not sure I see an alternative.  As
it is now, the lexer just hands the '#' directly to the parser and
then forgets about it, but it can't do that---succeeding text
like "1 'b x" is then truly ambiguous, and there is no way for
the lexer to know the right thing.  Maybe this issue should be
punted for now.  For this, I'm willing to change the source to
put in an explicit constant-size.

Cheers,
Peter Monta   pmonta@imedia.com
Imedia Corp.