Re: gEDA: Verilog: parse error

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

> module main;
>   reg a;
>   initial
>     a = #1 'bx;
> endmodule

pmonta@halibut.imedia.com said:
> Aha, I think the lexer is melding the delay and the constant, giving
> the nonsensical "a = #(1'bx);" to the parser.

Exactly.


pmonta@halibut.imedia.com said:
> but this is a real ambiguity then. Why doesn't the standard mention
> it?

Sure is, and the standard doesn't mention it, as far as I can tell.
The problem appears when the standard allows white space between
the size and the 'b.

It is possible to change the way that is parsed by taking the construction
of numbers out of the lexical analyzer. The parser can use context to
resolve this (though even there I see the potential for a shift-reduce
conflict.)

In short, I'm gonna punt on this for now.

 "a = #1 ('bx);" should work for you unambiguously.
-- 
Steve Williams                "The woods are lovely, dark and deep.
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