gEDA: Verilog: integer declarations, string bug?

[Peter Monta <pmonta-at-NOSPAMhalibut_dot_imedia_dot_com>]

With 19990911 a plain integer declaration, e.g.

module main;
  integer a;
endmodule

causes an assertion failure.  I'm not sure if the patch below
is correct---it may break the redeclare-task-port-as-integer
business---but it lets me compile ordinary stuff.

The pic.v microprocessor model is very close to compilable C++ now.
I've worked around the lack of $readmemh(), and there are only a
few casex's that I can convert manually to if-chains.  This pic.v
model is the largest open-source, complete, synthesizable Verilog
processor I've been able to find; it might be a nice accompaniment
to a first public release.  Nothing says "this is not a toy simulator"
better than "this nontrivial CPU simulates".  It can be found at

http://www.mindspring.com/~tcoonan/newpic.html

That low-level string bug is still present, so the C++ doesn't
quite compile (you have an earlier pic.v that still gives the
errors when run with 19990911).  Maybe I'll take a crack at it---
some sort of new/delete problem or string alias problem?
I don't know the C++-specific debugging stuff at all well, though.

Cheers,
Peter Monta   pmonta@imedia.com
Imedia Corp.

diff -ur verilog-19990911-orig/parse.y verilog-19990911/parse.y
--- verilog-19990911-orig/parse.y	Thu Sep  9 22:02:09 1999
+++ verilog-19990911/parse.y	Sat Sep 11 23:46:21 1999
@@ -173,7 +173,8 @@
 	| K_reg register_variable_list ';'
 		{ delete $2; }
 	| K_integer list_of_variables ';'
-		{ pform_set_reg_integer($2);
+		{ pform_makewire(@1, $2, NetNet::INTEGER);
+		  pform_set_reg_integer($2);
 		  delete $2;
 		}
 	;