gEDA: Problem with parametrized constant widths in VBS

[Ales Hvezda <ahvezda-at-NOSPAMseul_dot_org>]

[ Ales here, I'm reposting this since majordomo didn't recognize the
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Hello,

I've just tested my Verilog design with VBS simulator, and faced the strange
problem. After the thorough investigation, I've found the reason:
The VBS does not recognize correctly the parametrized constant's width.
Example:

   parameter        ws=3;
   reg [ws-1:0]     state_reg;
   parameter        IDLE = ws'h0, ADR = ws'h7, RD1 = ws'h6, RD2 = ws'h3,
                    WR1 = ws'h4, WR2 = ws'h5 ;

With such definitions, the "state_reg = ADR;" statement results in setting
state_reg to 3  =:-< ?!
Obviously the VBS interprets the ADR as "ws'h7", replaces the "ws" with 3,
but then reads the resulting "3'h7" as an integer without further analysis.
Probably this is a bug in VBS.
-- 
                        Greetings
                        Wojciech Zabolotny
                        http://www.ise.pw.edu.pl/~wzab

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