Re: gEDA: Problem with parametrized constant widths in VBS

[Jimen Ching <jching-at-NOSPAMflex_dot_com>]

On Tue, 18 Apr 2000, Steve Wilson wrote:
>Well - I put it through Verilog-XL.
>
>Error!    syntax error                                      [Verilog]
>          "test.v", 4: parameter        IDLE = ws'h<-
>
>That sort of answers the question in my mind ;-)

I guess this means I need to enhance VBS to detect this construct.  Odd
that bison didn't detect this and error out.

Thanks for looking into this, everyone.

--jc
--
Jimen Ching (WH6BRR)      jching@flex.com     wh6brr@uhm.ampr.org