gEDA: Icarus Verilog 20000421 Snapshot

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Bunches of bug fixes, and a few new features come with this snapshot.
This snapshot makes headway in both simulation and synthesis. I'm
also starting to make a big dent in my todo list for the 0.3 release.

    <ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000421.tar.gz>

The bunches of little bug fixes in this snapshot are a direct result of
bunches of bug reports this past week that I was able to deal with. If
you've been reporting bugs, this may contain your fix.

I redesigned the process implementation in the vvm backend, so the generated
code is a bit cleaner, and threads are lighter weight. And while I was at
it, fork/join now should work properly. I know there were a bunch of you
out there asking for this, so here it is.

I've incorporated into this release improved runtime support for integer
multiplication, it should now work now matter how incredibly enormous
you make the operands. Thanks to Chris Lattner for contributing the generic
multiply.

I've improved synthesis somewhat, there were some expressions in some
contexts that were not getting synthesized by the -Fsynth functor. This
is fixed, and I'm also starting to add some XNF specific optimizations
into the -Fxnfio functor. I do sensible things with identity compare,
for example.

I've added the program ``iverilog'' to be a new driver program written
in C instead of as a shell script. This driver supports the -tnull,
-txnf and -tvvm targets, as well as the -E flag that causes only the
preprocessor to be run. This should be interesting to those of you who
are looking for a working preprocessor. I'm still working on the -D and
the -I flags, but I expect this program to replace the verilog.sh script
before the 0.3 release.

And *finally* I got started on force/release. In fact, force assignments
should now work properly. Release isn't implemented yet, so it may be of
limited value, but I'm getting there.

WHAT'S NEXT

Well for one thing, release statements are next. force and release together
should get me a bunch more passing tests in the test suite. I may also
tackle assign/deassign as they are similar and should follow pretty obviously
from the force/release implementation.

I'm also expending some brain power on practical XNF synthesis in cooperation
with schematics generated from gschem. I'm working towards porting a non-
trivial XC4013XLA based design to gschem/Icarus Verilog so expect some
progress related to XNF synthesis. This particular task is motivating
some non-trivial XNF improvements in Icarus Verilog *and* gschem. Many
thanks to Ales for listening to my public ranting on the subject, we are
going to have a practical Xilinx design entry suite shortly!
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."