gEDA: User problems: Use of geda VERILOG tools to compile Lattice FPGA's?

[Wojciech Zabolotny <wzab-at-NOSPAMise_dot_pw_dot_edu_dot_pl>]

Hi All,

I'm trying to use gEDA tools to program Lattice FPGA's using the Verilog
language.
I'd like to compile my Verilog sources to the raw logical equations, and then
convert it to the form accepted by ispDesignExpert (I can do it eg. using the
relatively simple perl script to convert equations to ABEL).
However, I have still some problems:

1) VBS is not able to output the logical equations obtained from the verilog
   source. Is it?
2) The Icarus Verilog at the moment supports only the XNF format. It can't 
   be easily used by the "starter" version of ispDE, but maybe I'll find/write
   the conversion utility.
   However:
   The XNF output from Verilog sources sometimes doesn't work for me.
   Let's take the simplest example, the MUX.

When I implement it in the following form:

================ file mux,v ====================
module test_mux(in1,in2,sel,out);
`define width 8
  input [ `width -1 : 0 ] in1;
  input [ `width -1 : 0 ] in2;
  output [ `width -1 : 0 ] out;
  input sel;
  assign out = sel ? in1 : in2 ;
endmodule
================================================

I get the correct XNF output after: $verilog -X -s test_mux mux.v
However, when I implement it in the following way:

================= file test2.v =================
module test_mux(in1,in2,sel,outp);
`define width 8
  input [ `width -1 : 0 ] in1;
  input [ `width -1 : 0 ] in2;
  output [ `width -1 : 0 ] outp;
  input sel;
  reg [ `width -1 : 0 ] outp;
  always @(in1 or in2 or sel)
    begin
     if (sel==1)
	outp = in1;
     else
        outp = in2 ;
     end	
endmodule
================================================

I get the following errors:

wzab:~/wzplx$ verilog -X -s test_mux test2.v 
target (10target_xnf): Unhandled EVENT net node.
    event: anyedge test_mux._L3 --> test_mux._L2
        0 P<0> p: test_mux.in1[0]
        1 P<1> p: test_mux.in1[1]
        2 P<2> p: test_mux.in1[2]
        3 P<3> p: test_mux.in1[3]
        4 P<4> p: test_mux.in1[4]
        5 P<5> p: test_mux.in1[5]
        6 P<6> p: test_mux.in1[6]
        7 P<7> p: test_mux.in1[7]
target (10target_xnf): Unhandled EVENT net node.
    event: anyedge test_mux._L4 --> test_mux._L2
        0 P<0> p: test_mux.in2[0]
        1 P<1> p: test_mux.in2[1]
        2 P<2> p: test_mux.in2[2]
        3 P<3> p: test_mux.in2[3]
        4 P<4> p: test_mux.in2[4]
        5 P<5> p: test_mux.in2[5]
        6 P<6> p: test_mux.in2[6]
        7 P<7> p: test_mux.in2[7]
target (10target_xnf): Unhandled EVENT net node.
    event: anyedge test_mux._L5 --> test_mux._L2
        0 P<0> p: test_mux.sel[0]
target (10target_xnf): Unhandled proc_event.
    @(anyedge test_mux._L3 or anyedge test_mux._L5 or anyedge test_mux._L4) /* test_mux._L2 */
      if ((test_mux.sel)==('d1))
          test_mux._L0 = test_mux.in1;
      else
          test_mux._L1 = test_mux.in2;

The file test2.v simulates correctly with VBS and with Icarus Verilog

(I use the additional main module to perform the simulation:

module main;
  reg [`width -1 : 0] in1, in2;
  wire [`width -1 : 0] outp;
  reg sel ;
  testmux tt1(in1, in2, sel, outp);
  initial
    begin
      sel = 0; in1 =4; in2 = 5;
      $monitor("in1=%d, in2=%d, sel=%d, out=%d\n",in1,in2,sel,outp);
      #1; sel = 1;
      #1; in1 = 7;
      #1 ; sel = 0;
      #1 ; in2 = 10;
      #1 ; in1 = 1;
      #1 ; sel =1 ;
      #1;
    end
endmodule
)

So where is the problem? Is my second source wrong?
I've tried to compile it with the GPL'ed VER simulator/compiler, which
can generate the ABEL output and everything works fine...
However the VER seems to be less mature tool then Icarus Verilog and VBS,
and I had another troubles with it :-(.

And now a few final questions.
1) What precautions are necessary to write verilog sources, which can generate
   the XNF output with Icarus Verilog?
2) Are there any plans to add the ABEL backend to the Icarus Verilog?
   Is it difficult to add such a backend myself?
   Are the raw logical equations easily available somewhere in the IV's 
   internal data structures?
3) Are there any plans to include the VER compiler/simulator into the gEDA
   tools suite? I think it is worth of it, and it could speed up it's
   development. It is GPL'ed, and has some very interesting features,
   eg. the C based simulator, which is very useful when testing the more
   complicated modules...

-- 
			Thanks in advance, 
			Greetings
			Wojciech Zabolotny
			http://www.ise.pw.edu.pl/~wzab

http://www.debian.org  Use Linux - an OS without "trojan horses" inside