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Re: gEDA: User problems: Use of geda VERILOG tools to compile LatticeFPGA's?

To: geda-dev-at-NOSPAMgeda_dot_seul_dot_org
Subject: Re: gEDA: User problems: Use of geda VERILOG tools to compile LatticeFPGA's?
From: Jimen Ching <jching-at-NOSPAMflex_dot_com>
Date: Sat, 22 Apr 2000 10:54:18 -1000 (HST)
Delivery-Date: Sat, 22 Apr 2000 16:54:50 -0400
In-Reply-To: <20000422182133.A928@wzab.nasz.dom>
Reply-To: geda-dev-at-NOSPAMseul_dot_org
Sender: owner-geda-dev-at-NOSPAMseul_dot_org

On Sat, 22 Apr 2000, Wojciech Zabolotny wrote:
>1) VBS is not able to output the logical equations obtained from the verilog
>   source. Is it?

Correct.  VBS is a simulator, not a synthesis tool.  I assume that's what
you need.

--jc
--
Jimen Ching (WH6BRR)      jching@flex.com     wh6brr@uhm.ampr.org

References:
- gEDA: User problems: Use of geda VERILOG tools to compile Lattice FPGA's?
  - From: Wojciech Zabolotny

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