Re: gEDA: User problems: Use of geda VERILOG tools to compile Lattice FPGA's?

[Wojciech Zabolotny <wzab-at-NOSPAMise_dot_pw_dot_edu_dot_pl>]

On Sat, Apr 22, 2000 at 07:11:25PM -0700, Stephen Williams wrote:
> 
> What format do you want? What forms does ispDesignExpert accept?
> 

The "starter" version, which may be freely downloaded from Lattice
accepts only the "schematic" entry and the ABEL.
I think that the ABEL backend could be uselful also for other EPLD
devices...

> The raw logical equations are available to targets in the context of
> the netlist, and there are helper classes to scan them. Synthesized
> expressions are presented to the target as gates and nets, though.

Could you give me some pointers, how get the information just in that 
form (in fact the ABEL compiler may be fed with such information
after a small preprocessing <ie. building of nodes declarations, and
building of equations on the basis of netlist>).

Maybe the possibility to output the generated netlist in the ASCII
format would let us - the users, to create the "batch converters"
for different EPLD tools provided by IC manufacturers? 
I think that for many of us it could be easier to write the perl, or
python based program working as a postprocessor of IV generated netlist,
than to write the backend in C++ and to integrate it with rest of IV.
Such solution should be also more robust to changes occuring during the
development of IV. 

-- 
	                      Wojciech M. Zabolotny
	http://www.ise.pw.edu.pl/~wzab  <--> wzab@ise.pw.edu.pl

http://www.debian.org  Use Linux - save your data and time