Re: gEDA: [pmonta@terayon.com: Verilog version of OpenRISC 1001]

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Peter Monta <pmonta@terayon.com> said:
> I've translated the OpenRISC 1001 VHDL code to Verilog so I can play
> with it more easily.  It does seem to run most of the testbench code
> provided in the cpu_TB module, though the memory store gets skipped
> (does this happen with the VHDL as well?)

Yup, iverilog seems to simulate it:

	iverilog -s cpu_tb *.v
	./a.out

A quick visual inspection suggests that it might not be all that far
from being synthesizeable, too. Current synthesis is a bit finicky, though.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
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