gEDA: Icarus Verilog 20000428 Snapshot

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

This one clears up some pretty nasty and subtle bugs. If you've been
sending me bug reports, you're probably turning blue holding your breath
in anticipation of this snapshot. Breath in, Breath out.

    <ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20000428.tar.gz>

Hooray, both force and release work properly. I'm happy about that,
release worked out a bit easier then I expected. These should be useful
to test bench designers.

The big news this past week, however, has been bug fixes. Lots of bug
fixes. I got lots of bug reports and I killed pretty nearly all of
them. There were lots of nasty icky problems with passing parameters
to/from tasks, especially when memory words were involved. I fixed up
a whole bunch of these, and now parameter passing should work pretty
will, modulus the few remaining bugs I'm not seeing yet.

The iverilog command is in better shape now, and I encourage people
to use it in place of the older "verilog" driver script. There is a
man page for iverilog, and it supports all the switches needed to do
simulation and synthesis. I would like people to start getting this
driver well tested and the bugs worked out, because it is going to be
the main driver come the next stable release.

Some neat new XNF features are happening. I synthesize identity compare
in XNF, and a few other missing operators. But the really neato part is
that I've taught Icarus Verilog to generate PIN records for module
ports, so that you can make XNF macros out of Verilog source. If you
elaborate a module that has ports, the XNF code generator will automatically
generate the necessary symbols so that external XNF tools can link the
generated output into larger designs. I've compared the XNF files from
Icarus Verilog with those generated by Abel, and they appear the same
to my eyes.

WHAT'S NEXT

The assign/deassign statements are still missing. However, I'm not hearing
much of a clamor for them. I may put them aside for a while and work on
getting $random functional instead. I also hope to take a look at some
scope management issues related to tasks and functions. These need to
be handled better. There are some outstanding problems lurking here.

I'm also starting to think about supporting signed arithmetic. I've had
cause to wish I had it in my own work, so that gets my attention pretty
good. I already have the beginnings of support for signed numbers, so I
have a thread to pull to make it work.

And along the Xilinx front, I hope to get more operators to synthesize
efficiently in XNF, notably magnitude comparators. I'm also looking at
doing some simple CLB optimizations with FMAP devices. Since I'll be
personally using this in a professional environment, I should be aiming
for professional quality CLB utilization.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."