Re: gEDA: Re: "FREE" CPLD fitter tools

[graham-at-NOSPAMbelegost_dot_mit_dot_edu]

> 
> 
> You know what I think would be really nifty for synthesis? How 'bout
> if I could pass to the "assembler" a list of expression trees? I would
> like *something* that I can do programatically, instead of writing to
> a file and using the complete assembler, and a list of expressions I
> need anyhow even if I were to write the files.

Not totally sure what you mean here. Could you explain a bit more?
What I get from that is: you parse Verilog to generate expression
trees. libpal takes as input the expression trees and attempts to
fit them to the architecture, so that the fitter is moved into
the library (along, presumably, with the logic minimizer?).
What form are the expression trees? Only boolean
expressions, or do they still include arithmetic ops?

The way I'd originally envisaged this, before writing the current library
based version, was that reading data from files was only temporary,
and that at some point it would be linked in with other parts of gEDA
using guile (which I still have 0 experience of -  I'm only on about page
50 of SICP) as 'glue' to pipe data between parts. The current library
would be purely a backend.

Graham