gEDA: Icarus Verilog snapshot 20001119

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

Not to be outdone by Icarus PAL, here is a new snapshot for Icarus Verilog.

    <ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20001119.tar.gz>

The big change here (code wise) is improved and corrected constant
propagation. I was missing OR, NOR, NAND and XOR propagations, and
got some of the AND calculations wrong. This fixes this shortcoming
and in some cases this actually may speed up your compile a tiny bit.
Some more dangling signals are also eliminated.

supply nets are now working (PR#17). They also will trigger constant
propagation (as they have constant values) in certain cases.

Those of you doing cygwin compiles have trouble compiling parse.cc. I've
put into the cygwin.txt some slightly better instructions for dealing with
this situation, when it comes up.

I've also added missing symbols to ivl.def, so that tgt-stub properly
links.


WHAT'S NEXT

Icarus PAL is pretty well along now, so I'm starting to think about
the fitting process. Icarus Verilog already does enough synthesis to
make useful 22v10 designs, all that is left is for me to map combinational
logic to sum-of-products expressions, allocate pins and flop-flops, and
generate JEDEC files. This is still a couple snapshots away, probably.

I'm also catching up on pending bug reports. I'm going to try to fix
them *all* for the next stable release, which will come after PLD
synthesis is happening.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."