Re: gEDA: Unrolling sequential loops

[Magnus Danielson <cfmd-at-NOSPAMswipnet_dot_se>]

From: Ales Hvezda <ahvezda@seul.org>
Subject: gEDA: Unrolling sequential loops
Date: Sun, 26 Nov 2000 19:48:45 -0500

> 
> [ Ales here, I'm reposting this since majordomo didn't recognize the
>   e-mail as being subscribed to the geda-dev mailinglist. ]
> 
> -- Cut here --
> 
> Dear GEDA developers,

Dear Rainer,

> first of all, thanks for your great tools.
> 
> I am wondering, if the GEDA framework includes a tool for unrolling sequential 
> circuits at gate level. With unrolling sequential circuits I mean, if you have 
> a sequential circuit which obtains the input sequence I_i and generates the 
> output sequence O_i, the m time frames (=clock cycles) unrolled cicuit obtains 
> the inputs I_i concurrently and generates the outputs O_i of all m time frames 
> concurrently.
> 
> As an example, I drew the circuit below: It consists of a flip-flop and an and 
> gate.
> 
> 
>                   ---
> I_i ->--==========|&|--*---> O_i
>         |         ---  |
>         |              |
>         |     ----     |
>         ------|FF|<-----
>               ----
> 
> If I unroll m=2 time frames, this circuit with two inputs and two outputs is 
> obtained. The inputs of the even time frames of the original circuit are 
> applied to one of the inputs, the inputs of the odd time frames to the other. 
> Similar for the outputs.
> 
> 
>                   ---
> I_2i ->-==========|&|--*---> O_2i
>         |         ---  |                 ---
>         |              ------------======|&|--*---O_2i+1
>         |     ----                 |     ---  |
>         ------|FF|<---------       |          |
>               ----         |     I_2i+1       |
>                            |                  |
>                            |                  |
>                            --------------------

Sorry if I ask, but shouldn't there be a second FF in there?
The logic depth has increased from 1 to 2, and larger (say 32)
unrollings like this would not benefit from such a step.
Naturally, pre-processing of the signal has to be done...

I find the question as such as rather interesting, since having a tool
which you could do generic resynthesis of networks could be usefull.
Anyway, for most cases (PRBS, SSS, CRC etc) where this is important
you could synthesise the topology using well known algorithms anyway.

Cheers,
Magnus