gEDA: `include dependendencies in iverilog

[Steve Tell <tell-at-NOSPAMtelltronics_dot_org>]

Hi Steve, Hi to verilog users everywhere.
	
	On designs consisting of many verilog files, I have a need for a
tool to extract a list of the verilog "`include" dependencies in makefile
syntax.   

	I've prototyped this capability as a very simple patch to icarus
verilog.  Question for Steve:  Is the design described here, or somthing
like it, suitable for potential inclusion into standard iverilog? Question
for anyone:  Is this generally useful as-is?  Comments on a better way?

The idea is very much like the "-M" or "-MD" option to gcc.  Fortunately,
-M is available in both ivlpp and iverilog.   

proposal: new option -M <filename> added to both ivlpp and the iverilog.
driver.   If present, dependencies are written to the indicated file, but
verilog processing is not otherwise affected.   If it is desired to
generate dependencies only, the -E option to iverilog can be used, or 
a "-o /dev/null" can be passed to ivlpp.

Unfortunately is a little more complicated than that. In C, the target is
always a .o file, which depends on a single .c file and possibly whole
bunch of .h files.  The point being that the dependencies generated always
look like:
	foo.o: foo.c a.h b.h c.h ... 

In verilog, the target isn't so constrained; different users probably have
different conventions for the simulation-running makefiles.   So I don't
see any way but to add another option to set the target name that will
appear on the left of the colon.    Nor do I see any good mnemonic
option-letters that aren't already used in the iverilog driver.

final proposal:

if a.v contains "`include b.v", then this command:
	iverilog -M a.d -A a.log -t vvp -o a.vvp a.v
should produce two output files, the usual a.vvp and a dependency file
a.d which contains:

a.log: a.v b.v

The dependency file will use \ to continue long lines.  This file can be
directly read in to a makefile with make's "include" directive.

And this command
	iverilog -E -M a.d -A a.log a.v
will only produce the dependency file.   It should work even if the
verilog contains constructs that still cause iverilog to barf during
compilation or elaboration.


Comments?
If I sent this to you, Steve Williams, might you include it?

Steve Tell












--
Steve Tell  tell@telltronics.org