Re: gEDA: Icarus Verilog: Support for Xilinx Virtex Devices

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

terry@beam.demon.co.uk said:
> How well developed is the support for Xilinx Virtex devices in Icarus
> Verilog ? 

Not very. The EDF should be coming out right, but synthesis is a bit
weak. I'm hoping for this version cycle to do lots of related work,
even though the last few weeks have been slow.

But if it synthesizes, it should make a proper EDF file for virtex.
I think you are tripping on a bug, not a limitation.

terry@beam.demon.co.uk said:
> First problem is that normally in a Foundation 2.i constraint file I
> would use the pin named L17, however Icarus Verilog seems to only take
> a number and in the output EDF file prepends a "P" to the number. 

That seems like a simple bug. It is supposed to generate the right
attributes in the EDF file to hook up your pins.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

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