Re: gEDA: synthesizable Verilog style

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

ldoolitt@recycle.lbl.gov said:
> Is this good form?  Is it within the bounds that Icarus is on track to
> synthesize on or about v0.8?

This should already be synthesizeable by Icarus Verilog 0.7,
including the asynchronous reset. The -txnf target cannot
handle it, but the newer -tfpga should, modulus random bugs.


ldoolitt@recycle.lbl.gov said:
> Possibly related, how does Xilinx's usage of glbl.GSR relate to all of
> this? 

You need to instantiate a root level "glbl" module that contains
the GSR signal. Xilinx supplies such a module that you can use
in glbl.v.
-- 
Steve Williams                "The woods are lovely, dark and deep.
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