Re: gEDA: synthesizable Verilog style

[Larry Doolittle <ldoolitt-at-NOSPAMrecycle_dot_lbl_dot_gov>]

On Tue, Mar 11, 2003 at 03:49:10PM -0800, Stephen Williams wrote:
> ldoolitt@recycle.lbl.gov said:
> > Is this good form?  Is it within the bounds that Icarus is on track to
> > synthesize on or about v0.8?
> 
> This should already be synthesizeable by Icarus Verilog 0.7,
> including the asynchronous reset. The -txnf target cannot
> handle it, but the newer -tfpga should, modulus random bugs.

Cool.  I'll look for a way to confirm that.  The lowest
level of my code is, of course, riddled with instantiations
of Xilinx primitives.

> ldoolitt@recycle.lbl.gov said:
> > Possibly related, how does Xilinx's usage of glbl.GSR relate to all of
> > this? 
> 
> You need to instantiate a root level "glbl" module that contains
> the GSR signal. Xilinx supplies such a module that you can use
> in glbl.v.

Better still.  I can confirm that listing that root-level module
on the Icarus command line makes the warnings go away.

      - Larry