Re: gEDA: synthesizable Verilog style

[Steve Wilson <steve-at-NOSPAMspiketech_dot_com>]

Larry Doolittle wrote:

>On Tue, Mar 11, 2003 at 03:46:25PM -0800, Steve Wilson wrote:
>  
>
>>Larry - I would reformat it slightly for readability:
>>    
>>
>
>One man's treasure ...   ;-)
>
>  
>
>>always @(posedge clk40 or negedge rstn) 
>> if (~rstn) begin
>>       trace1_data <= 0;
>>    
>>
>
>As a habitual user of 8-wide <tab>s instead of spaces, I was looking
>for a way to _not_ indent the "meat" by two tabs.  Many of my lines of
>Verilog that do "real work" are too long already, thankyouverymuch.
>

Sounds like a personal problem to me ;-)

>
>  
>
>>       //*Concerning normal synth style:*
>>       *//if (trace_enable) address_at_pulse_end <= {5'b00000, 
>>       trace_address};
>>       //I would nominally pull this into a separage always block because of
>>       //the conditional load.   I might also rewrite it as below
>>       //if it were to remain as part of the block.
>>       //Larry - this is all cosmetic stuff I'm suggesting....
>>       *address_at_pulse_end <= trace_enable ? {5'b00000, trace_address}:
>>                                              address_at_pulse_end ;* 
>>    
>>
>
>It is (mostly) style that I'm asking about.  I'm a big fan of
>"say what you mean", and grouping related functionality where the
>maintainer can see everything at once.
>

As a practical matter - I would separate the last section into it's own 
always block if it remained coded as it was originally because it has a 
load requirement that the other guys don't have.  It's functionally 
different compared to the rest  of the elements in this always block. 

Well -we're talking verilog not C - so the styles aren't always 
co-incident.  I also learned Pascal BEFORE I learned see - so
I ACTUALLY would have been the following if I had coded it.

always @...
   if(~rstn)
      begin
      end
   else
      begin
       end

But I figured you didn't want to hear that ;-)  As for resets - I also 
tend to use "posedge reset" just cause it is easier to grep for negedge 
looking for flops clocked on the negedge (a bad thing many times..) So 
these are all personal preference but based on some experience as to 
preference.

Take care!

Steve




>
>If anyone here hasn't read Linus Torvalds' "Linux kernel coding
>style" document
>  .../linux-*/Documentation/CodingStyle
>it's worth checking out.  The irrational dogma is labeled as such,
>and correctly advises that practical needs can override any arbitrary
>guidelines in special cases.
>
>  
>
>>You "might" have an issue with the flops that the FPGA likes - if it 
>>only implements positive logic resets - then this
>>costs you.  Depends on what they like.  In some ASIC libs- this would be 
>>a bad idea cause they don't have active low resets.
>>    
>>
>
>The Xilinx Virtex data sheet says:
>  In addition to Clock and Clock Enable signals, each Slice
>  has synchronous set and reset signals (SR and BY). SR
>  forces a storage element into the initialization state speci-
>  fied for it in the configuration. BY forces it into the opposite
>  state. Alternatively, these signals can be configured to oper-
>  ate asynchronously. All of the control signals are indepen-
>  dently invertible, and are shared by the two flip-flops within
>  the slice.
>So it looks like any choice is safe in concept, with these parts.
>What is "standard practice", and why?
>
>        - Larry
>
>  
>