Re: gEDA: synthesizable Verilog style

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

ldoolitt@recycle.lbl.gov said:
> So it looks like any choice is safe in concept, with these parts. What
> is "standard practice", and why? 

Positive logic inside Xilinx FPGAs. Not all Xilinx FPGA families
give you the choice of input sense, but you are pretty safe with
positive logic.
-- 
Steve Williams                "The woods are lovely, dark and deep.
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