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Re: gEDA: synthesizable Verilog style

On Tue, Mar 11, 2003 at 04:18:47PM -0800, Steve Wilson wrote:
> 
> Well -we're talking verilog not C - so the styles aren't always 
> co-incident.

True.  I feel I should at least avoid making the same mistake twice.

>  I also learned Pascal BEFORE I learned see - so
> I[t] ACTUALLY would have been the following if I had coded it.
> 
> always @...
>   if(~rstn)
>      begin
>      end
>   else
>      begin
>       end
> 
> But I figured you didn't want to hear that ;-)

My history was Fortran -> C, with occasional detours to Algol,
assembly, APL, and other languages that are not worth remembering
(ratfor, anyone?).

>  As for resets - I also 
> tend to use "posedge reset" just cause it is easier to grep for negedge 
> looking for flops clocked on the negedge (a bad thing many times..)

Makes sense.  My 70% full XC2S150 has exactly one negedge clocked
Flip-Flop, and that one is used for a really strange and application-specific
purpose.

       - Larry