Re: gEDA: synthesizable Verilog style

[Hamish Moffatt <hamish-at-NOSPAMdebian_dot_org>]

On Tue, Mar 11, 2003 at 03:33:09PM -0800, Larry Doolittle wrote:
> always @(posedge clk40 or negedge rstn) if (~rstn) begin

[..]

> Is this good form?  Is it within the bounds that Icarus is on track to
> synthesize on or about v0.8?  Is "~rstn" or "!rstn" better?  Does the
> "negedge rstn" make sense?  How does Icarus pick the global reset net?

Just FYI, note that asynchronous reset inputs in Xilinx FPGAs are level
sensitive, not edge triggered. In VHDL we'd write this as

process (clk40, rstn)
begin
  if rstn = '0' then
    -- do reset stuff here
  elsif rising_edge(clk40) then
    -- do clocked stuff here
  end if;
end process;

Like the other suggestions you got for Verilog, it's standard to
completely seperate the reset and clocked stuff.

If you wanted a synchronous input, you wouldn't include it in the
sensitivity list (@always wouldn't mention the clock edge); you'd just
test for it inside, as in

process (clk40)
begin
  if rising_edge(clk40) then -- ignore the negative edge
    if rstn = '0' then -- synchronous reset
      -- reset condition
    else
      -- normal condition
    end if;
  end if;
end process;



Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>