Re: gEDA: A Plea for Programming Help (Icarus Verilog)

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

jrsheahan@optushome.com.au said:
> I'll volunteer to help with this. regressions in perl + verilog is
> something I've done before.

> just thinking though - this is formal verification land, rather than
> simulation.  could reducing the code work? 

Not quite. Formal verification is for verifying the Verilog, but
we are trying to verify the compiler. There are, I believe, subtle
differences. And I really want to go end to and and back again in
the tests of -tfpga so I really want something that compares the
Verilog with the mapped netlist fed through Xilinx tools. The
ngd2ver program seems the most likely tool here.

Anyhow, look at the ivtest project on sourceforge. I use the vvp_reg.pl
test rig almost daily, for example, and the vpi_reg.pl program as
well if I am working on stuff that might affect VPI.


-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."