Re: gEDA: A Plea for Programming Help (Icarus Verilog)

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

jdoege@inovys.com said:
> The problem with the proposed method is estabilishing correctness.
> That is, if you use simulation to validate work product, how do you
> know when you've simulated enough. Coverage tools are available, but
> they also cost $$$. Trivial test-cases for which coverage is easy to
> determine may not stress the compiler.

No need to over-analyze the problem. The way the existing test
suite works, is it is simply a non-decreasing collection of tests
with known expected results. A new bug is found, a new test gets
added to cover it. I often scrape the tests in the test suite from
bug reports. Synthesis tests should be collected in the same manner.

Talk of compiler coverage and the lot really can't be addressed,
because the internal construction of the compiler is not constant.
Even the evaluation of particular Verilog expressions varies amongst
contexts.

Ultimately, the only way to regression test a living compiler is
through sheer volume and variety in a test suite. And the only way
to manage that is to automate the checking the results of a run.
Gold files and/or self testing code are the techniques of use here.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."