Re: gEDA: A Plea for Programming Help (Icarus Verilog)

[Steve Wilson <steve-at-NOSPAMspiketech_dot_com>]

As the guy who should have written this - and hasn't had a chance to get 
to it (my wife had me putting up shelves this weekend for goodness sake 
- all other weekends have been spent at work :-(  I thought I could add 
a little bit here. 

Consider what you are suggesting.  Use of a $120K tool to validate a 
free tool.  Further, this is something that the main user, aka the other 
Steve, doesn't have daily or even ANY access to such tools.  Thus we get 
to role our own. 

The current validation harnesses are all variations on the original 
program contributed by Guy Hutchinson (if I recall his name correctly - 
don't have the code here to stare at it.) I've merely "enhanced" it this 
way or that to run the different environments we need. Steve is in need 
of something to run pretty much on a PC under Cygwin.  Perl is available 
on pretty much any environment - which is what has been used in the 
past.  There is nothing that says it can't be something else, just this 
is the history - and perl is everywhere as a tool.

If I get time - I would do this - but I've been trying to find that time 
for at least 3 months now!  If anyone else can step up to this - PLEASE 
FEEL EMPOWERED to go for it.  If you want the Icarus simulation ->Icarus 
Synthesis -> Xilinx P&R path to work reliably this is the VERY BEST 
place to add your contribution to the better than 3 man years of effort 
Mr. Williams has already contributed to this project.  

Best regards,

Steve Wilson

Jason Doege wrote:

>Actualy, one could use formal to validate the compiler. Run the test
>circuit through XST and through Icarus, then formally compare the two
>results. Also, I think some formal tools permit RTL<->Gates comparison.
>
>The problem here is the cost of the tools and the non-trivial nature of
>writing a formal verification tool which uses synthesis, ATPG, fault
>simulation, expert systems and other complex technologies to do what
>they do.
>
>The problem with the proposed method is estabilishing correctness. That
>is, if you use simulation to validate work product, how do you know when
>you've simulated enough. Coverage tools are available, but they also
>cost $$$. Trivial test-cases for which coverage is easy to determine may
>not stress the compiler. Exhaustive testing of sequential circuits can
>be, well, exhausting.
>
>I am also willing to contribute to this project. Perl hacking, I can do
>and, given a set of test goals, I can readily provide verilog code to
>stress the compiler. I already do, actually. Unfortunatly they are of
>the dump core variety.
>
>Best regards,
>Jason
>
>
>
>-----Original Message-----
>From: Stephen Williams [mailto:steve@icarus.com] 
>Sent: Monday, March 24, 2003 9:07 AM
>To: geda-dev@seul.org
>Subject: Re: gEDA: A Plea for Programming Help (Icarus Verilog) 
>
>
>
>jrsheahan@optushome.com.au said:
>  
>
>>I'll volunteer to help with this. regressions in perl + verilog is 
>>something I've done before.
>>    
>>
>
>  
>
>>just thinking though - this is formal verification land, rather than 
>>simulation.  could reducing the code work?
>>    
>>
>
>Not quite. Formal verification is for verifying the Verilog, but we are
>trying to verify the compiler. There are, I believe, subtle differences.
>And I really want to go end to and and back again in the tests of -tfpga
>so I really want something that compares the Verilog with the mapped
>netlist fed through Xilinx tools. The ngd2ver program seems the most
>likely tool here.
>
>Anyhow, look at the ivtest project on sourceforge. I use the vvp_reg.pl
>test rig almost daily, for example, and the vpi_reg.pl program as well
>if I am working on stuff that might affect VPI.
>
>
>  
>