Re: gEDA: A Plea for Programming Help (Icarus Verilog)

[Stephen Williams <steve-at-NOSPAMicarus_dot_com>]

jdoege@inovys.com said:
> Actualy, one could use formal to validate the compiler. Run the test
> circuit through XST and through Icarus, then formally compare the two
> results. Also, I think some formal tools permit RTL<->Gates
> comparison. 

Actually, now that I think about it, I don't want to match xst bugs
(if they turn up) and the output from ngd2ver may not be suitable
for this sort of verification anyhow. It's OK for a human to make
the initial determination that the output is correct, even if that
involves comparison with the pre-synthesis results, then using the
expected output as a gold standard. Low tech, but workable. Witness
the existing vvp_reg.

I also don't want to require anything more then what's available
in the WebPACK and/or Cygwin, when running under Windows.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."