gEDA: Icarus Verilog: Is it bug??

[DP Narendra <ndevtapr-at-NOSPAMengineering_dot_uiowa_dot_edu>]

Hi,

I found this bug when trying to simulate a simple verilog file.
I am assigning a reg in a if statement where the condition is x, but the 
reg gets assigned 0 (in the false part of statement). The reg is not 
assigned anywhere else.

I am attaching a simple file that illustrates this bug. Is this a valid 
bug?


module bug;

wire a, b;
reg c, d;

assign a = x;
assign b = x;

always @(posedge c)
if (a & ~b)
   d = 1'b1;
else
   d = 1'b0;

initial
  begin
    #1 c = 0;
    #1 c = 1;
    #1
    if ((d == 1'b1) || (d == 1'b0)) 
        $display("FAILED\n");
    else 
        $display("PASSED\n");
    
    $finish;
  end

endmodule