RE: gEDA: Icarus Verilog: Is it bug??

["EATON,JOHN (HP-Vancouver,ex1)" <john_eaton-at-NOSPAMhp_dot_com>]

Cadence verilogXL gives Error!  Identifier (x) not declared.


It's not a bug. "a" and "b" are unknown so the "if" will fail and
the "else" will resolve to a 0. I'ts easy to write code that resolves
x's to a known value. It is also dangerous. Thats why we always check
our designs by runing the same sims on the compiled gates. 

John Eaton


-----Original Message-----
From: DP Narendra [mailto:ndevtapr@engineering.uiowa.edu]
Sent: Tuesday, April 08, 2003 9:00 PM
To: geda-dev@seul.org
Subject: gEDA: Icarus Verilog: Is it bug??


Hi,

I found this bug when trying to simulate a simple verilog file.
I am assigning a reg in a if statement where the condition is x, but the 
reg gets assigned 0 (in the false part of statement). The reg is not 
assigned anywhere else.

I am attaching a simple file that illustrates this bug. Is this a valid 
bug?