Re: gEDA: Icarus Verilog: Is it bug??

[DP Narendra <ndevtapr-at-NOSPAMengineering_dot_uiowa_dot_edu>]

Thanks for the clarification. I was thinking of how the code will behave 
when synthesized into gates. As pointed out in previous mail, it will 
create a simulation-synthesis mismatch.



On Wednesday 09 April 2003 10:55 am, Stephen Williams wrote:
> ndevtapr@engineering.uiowa.edu said:
> > I found this bug when trying to simulate a simple verilog file. I am
> > assigning a reg in a if statement where the condition is x, but the
> > reg gets assigned 0 (in the false part of statement). The reg is not
> > assigned anywhere else.
>
> IEEE1364-2001 Section 9.4 Conditional statement
>
>  "If the expression evaluates to true (that is, has a nonzero known
>  value), the first statement shall be executed. If it evaluates to
>  false (has a zero value or the value is x or z), the first statement
>  shall not execute. If there is an else statement and expression is
>  false, the else statement shall be executed."
>
> In other words, the conditional (if) statement will execute either
> the true clause or the false clause. Unknown values are treated as
> false.