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Re: gEDA: Icarus Verilog: Is it bug??

To: geda-dev-at-NOSPAMseul_dot_org
Subject: Re: gEDA: Icarus Verilog: Is it bug??
From: Stephen Williams <steve-at-NOSPAMicarus_dot_com>
Date: Wed, 09 Apr 2003 11:10:23 -0700
Delivery-Date: Wed, 09 Apr 2003 14:10:40 -0400
In-Reply-To: Your message of "Wed, 09 Apr 2003 10:25:37 PDT." <3E945791.40806@pacbell.net>
Reply-To: geda-dev-at-NOSPAMseul_dot_org
Sender: owner-geda-dev-at-NOSPAMseul_dot_org

     this <= #1 (reset) ? 0 : that;
     foo  <= #1 (reset) ? 0 : bar;

frustum@pacbell.net said:
> if reset is 'bx, then this and foo will both get set to 'x. 

Not quite. If that is 0, then this will get 0, no matter what
reset is. Same for bar and foo.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Follow-Ups:
- Re: gEDA: Icarus Verilog: Is it bug??
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References:
- Re: gEDA: Icarus Verilog: Is it bug??
  - From: Jim Battle

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